1. Field of the Invention
The present invention relates generally to the field of methods and circuits for digital to analog conversion. More particularly, the present invention relates to a method and circuit for digital to analog signal conversion using sigma-delta modulation of the temporal spacing between digital samples.
2. Discussion of the Related Art
Digital to Analog Converter (DAC) circuits and methods for digital to analog conversion are well-known in the art. Conventional DACs receive a binary level single or multi-bit digital signal on an input terminal(s) and, as a function of a reference voltage, convert the digital signal into a corresponding analog signal.
One type of DAC that has recently become popular is the so-called sigma-delta DAC. There are many references describing sigma-delta systems. One example is entitled Mixed-Signal Design Seminar published by Analog Devices, Inc., 1991, which is incorporated herein by reference.
As shown in FIG. 1, a conventional sigma-delta digital to analog converter includes an interpolation filter 1 that increases the sample rate (i.e. data rate or sampling frequency) of a digital input signal by some predetermined oversampling ratio to a higher sampling rate and rejects any signal images that occur at approximately the Nyquist rate of the input signal. The higher rate digital signal is then transmitted to a sigma-delta modulator 2 that noise shapes the digital data stream and reduces the sample width to one bit. In digital to analog converters, the sigma-delta modulator is typically all digital. The sigma-delta modulator effectively low pass filters the signal of interest and high pass filters the quantization noise on the signal. The output of the sigma-delta modulator is typically a high frequency one-bit data stream. The one-bit DAC 3 receives the modulator output and provides a corresponding analog signal that is either plus or minus full scale. The output of the one-bit DAC is transmitted to an analog smoothing filter 4 that averages the output of the one-bit DAC and removes the shaped quantization noise that resides in the upper frequency area.
One of the limitations of conventional DACs including the sigma-delta DAC illustrated in FIG. 1 is that they only determine the magnitude of the input signal at equally spaced temporal intervals. This is known as uniform sampling. Additionally, in conventional DACs, the sample rate, that is, the data rate of the incoming digital data stream cannot be independent of the master clock that is used to clock the DAC. The incoming digital data rate must be some integer division of the master clock on the DAC chip. This means that if the DAC were to receive digital data at two different data rates, that are not necessarily divisible into the master clock (or more generally, digital data at a rate that is not integrally divisible into the master clock), there must be two different frequency master clocks available for clocking the DAC (or more generally, there must be a master clock that has an integer relationship with the data rate of the incoming digital data available to clock the DAC).
Another problem with conventional DACs is that they typically are not designed to be clocked by an externally supplied clock signal. The components of the DAC are typically optimized to operate at the clock frequency determined by the master clock on the DAC chip. This leads to the additional limitation that some DACs cannot lock to and operate at some externally supplied clock signal. Therefore, if there are any changes in the digital data rate, since the incoming digital data stream and the master clock for the DAC are not necessarily related to each other, any changes in the relative frequencies of the data rate and the master clock can disrupt the entire digital to analog conversion process.
Therefore, an object of the present invention is to provide a method and apparatus for performing digital to analog conversion using non-uniform sampling (i.e., variable temporal spacing of the sampling points).
Another object of the present invention is to provide a method and apparatus for performing digital to analog conversion that can lock to an externally supplied clock signal and can provide a sampling rate that is independent of the DAC master clock.